The present invention relates to flip-flops and, more particularly, to those which operate on principles consonant with the master/slave technique.
The circuit has been designed to achieve fast data thruput while eliminating the timing hazards associated with skew in a clock pulse, which hazards are known to produce inaccurate results in digital counters and the like. The invention is particularly suitable for realization in the form of an integrated circuit. More specifically, the circuit of the present invention is preferably realized in large scale integration of emitter-coupled-logic gate arrays.
Logic design for the structuring of the basic hardware architecture of digital systems has evolved through various stages of sophistication closely correlated with increased efficiency and design in manufacture of the basic media of implementation. Small to medium scale circuit integration techniques have provided adaptable logic on a chip permitting progressively more complex series gating in implementing families of logic functions tailored to specific needs.
In architectures employing small to medium scale integration (SSI/MSI), the measure of flexibility has been viewed as a function of the specific molecular electronic technology selected. For example, emitter-coupled logic implementations (ECL) have been characterized both by facile design of series or stacked gates and by the availability of complementary outputs at each gate or logic level. In contradistinction, transistor-to-transistor implementations (TTL) have tended to be more complex for the reason that the complementary output is not always available. Aside from considerations of flexibility, ECL is inherently faster than TTL while only slightly more expensive.
More recently there has evolved an alternative to SSI/MSI structured architecture. In developing architectures employing the alternative, large scaled integration (LSI), critical design parameters have been speed and flexibility. Although ECL does not lend itself to series gating when employing LSI techniques, the combination of ready availability of complementary outputs and greater speed has tended to indicate its selection over alternatives. However, problems have arisen in attempting to implement ECL SSI/MSI series logic circuits by LSI techniques. These problems derive principally from factors associated with cost and operating environment such as overheating.
A secondary constraint has derived as a material consequence of the migration away from series gating in ECL LSI implementations. Limitations are found in the number of functions or, more precisely, combinations of elements to define functions that may be implemented without introducing timing hazards, i.e., conditions wherein both a clock pulse and its complement may be apparent in a logic circuit at the same time. These conditions may give rise to signal race conditions, i.e., propagation of signals through a system toward plural destinations resulting in spurious data signals reflecting these ambiguous cases. These problems, again, are consequential and exist by virtue of the fast operation, i.e., fast clocking of systems embodying ECL LSI circuits.
The present inventive master/slave flip-flop maintains speed and flexibility of LSI logic circuit implementations while eliminating timing hazards associated with skew of clock pulses, i.e., offset of a clock pulse with respect to its complement in systems embodying such circuits.